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  applications -  automotive panels  machine tools  atm machines  touch-screens  appliance controls  outdoor keypads  security keypanels  industrial keyboards the qt60320 digital charge-transfer (?qt?) qmatrix? ic is designed to detect touch on up to 32 keys in a scanned x-y matrix. it will project the keys through almost any dielectric, like glass, plastic, stone, ceramic, and even most kinds of wood, up to thickne sses of 5 cm or more. the touch areas are defined as simple 2-part interdigitated electrodes of conductive material, like copper, indium-tin-oxide (ito), or screened silver or carbon deposited on the rear of the control panel. key sizes, shapes and placemen t are almost entirely arbitrary; sizes and shapes of keys can be mixed within a single panel of keys and can vary by a factor of 20:1 or more in area. the gain (sensitivity) and threshold of each key can be set individually via simple commands over the uart port, for e xample via the freeware qmbtn program. key setups are stored internally in an onboard eeprom and do not need to be reloaded. the ic is designed specifically to work with appliances, atm machines, security panels, portable instruments, machine tools, or similar products that are subject to environmental 'challenges' or even physical attack. it permits the construction of 100% se aled, watertight keypanels that are immune to environmental factors such as humidity and condensation, temperature, dirt accumulation , or the physical deterioration of the panel surface from abrasion, chemicals, or abuse. to this end the qt60320 contains quantum-pioneered self-calibration, drift compensation, and digital filtering algorithms that make the sensing function extreme ly robust and survivable. the device can readily control keys over graphical lcd panels or leds when used with clear, conductive ito electrodes. it does not require 'chip on glass' or other exotic fabrication techniques, thus allowing the oem to source the keymatrix from multiple ven dors. external circuitry consists of an opamp, a common pld, and a quad fet switch, which can fit into a footprint of roughly 1 squar e inch (6.5 sq. cm). the device also can control two status leds, and includes in addition 8 addressable output drive lines and 4 read able spare input lines which can be used to control leds, lcds, or other panel functions without requiring additional control lines from the host cpu. it also makes available to the user 86 bytes of onboard writeable and readable eeprom via the serial interface, thus helping to reduce system cost by eliminating extra components. qt60320 technology makes use of an important new variant of charge-transfer sensing, transverse charge-transfer, in an xy forma t that minimizes the number of required scan lines. unlike older technologies it does not require one ic per key, and is cost com petitive even with some membrane technologies. in many cases it can also replace resistive xy sense elements commonly used in touch screens, at a fraction of the price. this part is not recommended for new designs. consult quantum for advice on alternatives. lq copyright ? 1999, 2001 quantum research group ltd qt60320c r1.08/01.03 l q qt60320c not recommended for new designs 32-k ey qm atrix ? c harge -t ransfer ic  creates 32 ?touch buttons? through any dielectric  100% autocal for life - no adjustments required  'n' key rollover: senses all 32 keys in parallel  keys individually adjustable for sensitivity  mix 'n match key sizes & shapes in one panel  tolerates a 20:1 variance in key sizes on a panel  panel thicknesses to 5 cm or more  back lit keys possible with ito electrodes  led status function drives  user-addressable multifunction drive pins  user-addressable internal eeprom  simple, universal serial interface  5v single supply operation  44-pin tqfp package  one square inch (6.5 square cm) of pcb required x5 x4 x3 x2 x1 gnd vcc ain i4 i3 i2 o2 o3 o4 l1 l2 vcc gnd y1 y2 y3 y4 x6 x7 x8 rst vcc gnd xt2 xt1 rx tx o1 o5 o6 o7 o8 vcc agnd aref cs cc2 cc1 i1 1 2 3 4 5 6 7 8 9 10 11 23 24 25 26 27 28 29 30 31 32 33 44 43 42 41 40 39 38 37 36 34 35 12 13 14 22 21 19 20 18 17 16 15 qt60320 QT60320C-AS -40 0 c to +105 0 c tqfp t a available options
1 - overview the qt60320 is a digital burst mode charge-transfer (qt) sensor designed specifically for matrix geometry touch controls; it includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions. only a few low cost external parts are required for operation. the entire circuit can be built within about 1 square inch of pcb area (smt). the 60320 uses burst-mode charge transfer methods pioneered and patented by quantum, including charge cancellation methods which allow for a wide range of key sizes and shapes to be mixed together in a single keypanel. these features permit the construction of entirely new classes of keypanels never before contemplated, such as touch-sliders, back-illuminated keys, and arbitrary shape keypanels, all at very low cost. the qt60320 uses an asynchronous serial (uart) interface running at 9600 baud to allow key data to be extracted and to permit individual key parameter setup. the interface protocol uses simple ascii commands and responds with either ascii or binary results depending on the command. in addition to normal operating and setup commands the device can also report back actual key signal strength and error codes. spare eeprom memory (over 80 bytes) can also be written to and read to save the system designer from having to install and interface to a separate eeprom. the ic also includes 4 readable input (i1..i4) pins and 8 settable output (o1..o4) pins which can be used in any way desired, including to scan a secondary keypad of up to 32 contact closures. alternatively they can be used to remotely activate panel leds, buzzers, or other types of indicators. qmbtn software for the pc can be used to program a board containing the ic as well as read back key status and signal levels in real time. the qt60320 employs transverse charge-transfer ('qt') sensing, a new technology that senses the charge forced across an electrode set by a digital edge. 1.1 field flows figure 1-1 shows how charge is transferred across the electrode set to permeate the overlying panel material; this charge flow exhibits a rapid dq/dt during the edge transitions of the x drive pulse. the charge emitted by the x electrode is partly received onto the corresponding y electrode which is then processed. the qt60320 matrix uses 8 'x' edge-driven rows and 4 'y' sense columns to allow up to 32 keys. the charge flows are absorbed by the touch of a human finger (figure 1-2) resulting in a decrease in coupling from x to y; coupled charge increases in the presence of a conductive film like water (figure 1-3) which acts to bridge the two elements. increasing signals due to water films are quite easy to discern and are not detected by the ic. 1.2 circuit model an electrical circuit model is shown in figure 1-4. the coupling capacitance between x and y electrodes is represented by cx. while the reset switch is open, a sampling switch is gated so that it transfers charge flows only from the rising edge of x into the sample capacitor cs. cs is a large value capacitor, typically in the range of 1 - 50nf. the voltage rise captured on cs after each x edge is quite small, on the order of a millivolt, while changes due to touch are on typically the order of 10's of microvolts. the x pulse can be repeated in a burst consisting of up to several hundred pulses to build up the voltage (and the change in voltage due to touch) to a larger value. longer bursts increase system gain by collecting more charge; gain can thus be digitally manipulated to achieve the required sensitivity on a key-by-key basis during scanning. if the voltage on cs rises excessively it can fall outside of the adc's range. to reduce the voltage again without affecting gain, one of two (or both) cz capacitors can be switched to l q 2 qt60320c r1.08/01.03 figure 1-2 field flows when touched figure 1-3 fields with a conductive film overlying panel x element y element figure 1-1 field flow between x and y elements overlying panel x element y element
subtract charge from cs to create a negative-going offset, bringing the signal back to a usable level. this action occurs during the course of the burst and is not illustrated in the timing diagram of figure 1-4. this mechanism has the benefit of allowing high levels of cx while remaining highly sensitive to small changes in charge coupling due to touch; the circuit permits the designer to create very large, highly interdigitated touch keys that are very sensitive. the large cs capacitor creates a virtual ground termination, making the y lines appear as a low impedance; this effectively eliminates cross-coupling among y lines due to voltage spikes, while dramatically lowering susceptibility to emi. the circuit is also highly tolerant of capacitive loading on the y lines, since stray c from y to ground appears merely as a parallel capacitance to a much larger value of cs. the qt60320 circuit design maintains high gain levels independent of cx or stray coupling c to ground. it also readily compensates for field-related issues like electrode design or the composition of the overlying panel, as it has individual programmable gain and threshold settings for each key. short sample gate dwell times after the x edge can be used to limit the effect of moisture spreading from key to key by taking advantage of the rc filter-like nature of continuous films; the shorter the dwell time, the less time that the charge has to travel through the impedance of the film. this effect is completely independent of the frequency of burst repetition, intra-burst pulse spacing, or x drive pulse width. burst mode operation permits reduced power consumption and reduces rf emissions, while permitting excellent response time. 1.3 matrix configuration the matrix scanning configuration is shown in part in figure 1-5. the x drives are conventional cmos push-pull outputs which are sequentially pulsed in groupings of bursts; a 4-pole analog switch acts as the sample switch for all 4 y lines. at the intersection of each x and y line is an interdigitated electrode set as shown in figure 1-6. typically the outermost electrode is connected to x and the inner electrode connected to y. remaining y lines not being sampled are grounded. 1.4 'x' electrode drives the 8 'x' lines can be directly connected to the matrix without buffering. only the x lines' positive edges are used to create the transient field flows used to scan the keys. only one x line is active at a time, and it will pulse for a burst length determined by the 'gain' setting parameter. if desired an external 22v10 type cmos pld can be used to create the short gate dwell times necessary to enhance moisture suppression (section 1.2). the pld takes as its input all 'x' and 'y' lines, and with added rc time constants creates the required short dwell time on the y switches. the code for the pld is available freely on the quantum web site and can also be found in section 5. 1.5 'y' gate drives there are 4 'y' gate drives (y1..y4) which are active-high; only one y line is used during a burst for a particular key. the chosen y line goes high just before an x line transitions high, and goes low again just after the x line rises. it is used to gate on an analog switch, such as a 74hc4066, to capture charge coupled through a key to the sample capacitor cs. an inverted version of the y lines can be used to gate unselected y lines to ground, to suppress residual cross-key coupling that might be caused by cross-pickup from adjacent x drive traces. see section 2.2. y gate signals can be manipulated externally so that the gate dwell time is very short to suppress the effects of surface conductivity due to water films. see section 2.3. l q 3 qt60320c r1.08/01.03 figure 1-4 qt60320 circuit model out v amp 0 0 1 1 0 x drive (1 of 8) y receive line (1 of 4) x electrode y electrode sample switch (1 of 4) cx cs reset switch cz (1 of 2) cancellation switch (1 of 2) 8-bit adc x drive reset switch sample switch amp out figure 1-5 qt60320 matrix configuration x 1 x 2 x 3 x 4 y adc y s1 y s2 y s3 y s4 1 y 2 y 3 y 4 cs reset switch interdigitated keys x drives (4 of 8 shown)
1.6 signal processing the qt60320 calibrates and processes all signals using a number of algorithms pioneered by quantum. these algorithms are specifically designed to provide for high survivability in the face of adverse environmental challenges. 1.6.1 s elf -c alibration the qt60320 is fully self-calibrating. on powerup the ic scans the matrix key by key and sets appropriate calibration points for each in accordance with setup information in its internal eeprom, or on the fly from a host mpu. since the circuit can tolerate a very wide dynamic range, it is capable of adapting to a wide mix of key sizes and shapes having wildly varying cx coupling capacitances. no special operator or factory calibration or circuit tweak is required to bring keys into operation, except for a gain and threshold batch setup which can be performed in seconds from a file saved on a pc. once set, there should never be a need to readjust these parameters. 1.6.2 d rift c ompensation a lgorithm signal drift can occur because of changes in cx and cs over time. it is crucial that drift be compensated for, otherwise false detections, non-detections, and sensitivity shifts will follow. drift compensation (figure 1-7) is performed by making the reference level track the raw signal at a slow rate, but only while there is no detection in effect. the rate of adjustment must be performed slowly, otherwise legitimate detections could be ignored. the qt60320 drift compensates using a slew-rate limited change to the reference level; the threshold and hysteresis values are slaved to this reference. when a finger is sensed, the signal falls since the human body acts to absorb charge from the cross-coupling between x and y lines. an isolated, untouched foreign object (a coin, or a water film) will cause the signal to rise slightly due to the enhanced coupling thus created. these effects are contrary to the way most capacitive sensors operate. once a finger is sensed, the drift compensation mechanism ceases since the signal is legitimately low, and therefore should not cause the reference level to change. the qt60320's drift compensation is 'asymmetric': the drift-compensation occurs in one direction faster than it does in the other. specifically, it compensates faster for increasing signals than for decreasing signals. decreasing signals should not be compensated for quickly, since an approaching finger could be compensated for partially or entirely before even touching the sense pad. however, an obstruction over the sense pad, for which the sensor has already made full allowance for, could suddenly be removed leaving the sensor with an artificially suppressed reference level and thus become insensitive to touch. in this latter case, the sensor will compensate for the object's removal by raising the reference level quickly. 1.6.3 t hreshold and h ysteresis c alculations the threshold value is established as an offset to the reference level. as cx and cs drift, the reference drift compensates with the changes and the threshold level is automatically recomputed in real time so that it is never in error. since key touches result in negative signal swings, the threshold is set below the signal reference level. the qt60320 employs a hysteresis of 25% of the delta between the reference and threshold levels. the signal must rise by 25% of the distance from threshold to reference before the detection event drops out and the key registers as untouched. 1.6.4 m ax o n -d uration if a foreign object contacts a key the signal may change enough to create a 'false' detection lasting for the duration of the contact. to overcome this, the ic includes a timer which monitors detection duration. if a detection exceeds the timer setting, the timer causes the sensor to perform a full recalibration. this is known as the max on-duration feature. after the max on-duration interval has expired and the recalibration has taken place, the affected key will once again function normally even if still contacted by the foreign object, to the best of its ability. the max on-duration is fixed at 10 seconds of continuous detection. 1.6.5 d etection i ntegrator to suppress false detections caused by spurious events like electrical noise, the qt60320 incorporates a detection integration counter that increments with each detection sample until a limit is reached, at which point a detection is confirmed. if no detection is sensed on any of the samples prior to the final count, the counter is reset immediately to zero, forcing the process to restart. the required count is 4. 2 - circuit specifics a basic qt60320 circuit is shown in figure 2-1. 2.1 signal path the qt60320 requires an external sampling capacitor, two cz capacitors, an amplifier, some analog switches, and an r2r ladder dac to operate. the cs capacitor performs the charge integration function by collecting charge coupled though a selected key during the l q 4 qt60320c r1.08/01.03 figure 1-7 drift compensation threshold signal hysteresis reference output figure 1-6 sample electrode geometries parallel lines serpentine spiral
dv/dt of the rising edge of an 'x' scan line. the charge is sampled 'n' times during the course of a burst of switching cycles of length 'n'. as the burst progresses the charge on cs increases in a staircase fashion (figure 1-4). at the burst's end the voltage on cs, which is on the order of a few tenths of a volt, is amplified by a gain circuit which includes an offset current from the r2r ladder dac driven by the x drive lines. the offset current from the r2r ladder repositions the output of the amplifier chain to coincide as closely as possible with the center span of the 60320's adc, which can convert voltages between 0 and 5 volts. between bursts the cs reset mosfet is activated to reset the cs capacitor to ground. gain is directly controlled by burst length 'n', amplifier gain av, and the values of cs, cz1 and cz2. only 'n' can be adjusted on a key by key basis whereas av and the capacitances can only be adjusted for all keys. the amplifier should typically have a total positive gain of 100 +/- 20%.. if there is a large amount of coupling between x and y lines, and where burst length 'n' is set to a high number, charge accumulation on cs may reach a point where the ladder dac can no longer offset the signal back into the adc's usable range. in this case the circuit will employ one or two of the cz capacitors to 'knock back' or cancel the charge accumulated on cs; each cz will cancel charge in a discrete step as required. components shown in figure 2-1 include:  an lvd reset (e.g. dallas ds1811) suitable for 5 volt supplies and an active-low on low-voltage output;  an r2r ladder network (cts 750-107r100k or equivalent);  a >2mhz gbw cmos rail-rail output opamp capable of sensing ground on the inputs;  an 8mhz crystal or resonator, or a ceramic resonator with built-in capacitors;  two indicator leds (optional) to show sensing state and calibration status;  74ac04 inverters to drive the two banks of analog switches in opposite states;  two 74hc4066 analog switches;  a reset mosfet, most any small-signal mosfet with a guaranteed on-state at 4 volts l q 5 qt60320c r1.08/01.03 figure 2-1 basic qt60320 circuit x1 x2 x3 x4 x5 x6 x7 x8 ys1 ys2 ys3 ys4 cc1 cc2 cs ain gggg vvv vcc vcc rst rx tx i1 i2 i3 i4 o1 o2 o3 o4 o5 o6 o7 o8 xt1 xt2 l1 l2 4 9 10 33 34 35 36 11 12 13 14 23 24 25 26 8 7 15 16 618 39 v 51727 38 40 41 42 43 44 1 2 3 19 20 21 22 32 31 30 37 28 29 ds1811 8mhz cal led stat led c6 (cz1) 820pf c7 (cz2) 820pf bsn20 r2r dac 100k + _ + _ r3 68k r5 10k r4 100k r6 10k c5 (cs) 15nf vcc 1/4 hc4066 1/4 hc4066 1/4 hc4066 1/4 hc4066 tlc2272 qt60320 user po rt pins uart in uart out v keymatrix y3 y2 y4 y1 1/4 hc4066 1/4 hc4066 1/4 hc4066 1/4 hc4066 74ac04 figure 2-2 improved circuit to suppress water films x2 x3 x4 x5 x6 x7 x8 ys1 ys2 ys3 ys4 cc 1 cc 2 cs ain gggg vv v vcc vcc rst rx tx i1 i2 i3 i4 o1 o2 o3 o4 o5 o6 o7 o8 xt1 xt2 l1 l2 4 9 10 33 34 35 36 11 12 13 14 23 24 25 26 8 7 15 16 618 39 v 51727 38 40 41 42 43 44 1 2 3 19 20 21 22 32 31 30 37 28 29 ds1811 8mh z cal led stat led c6 (cz1) 820pf c7 (cz2) 820pf bsn20 r2r dac 100k r3 68k r5 10k r4 100k r6 10k c5 (cs) 15nf vcc tlc2272 qt60320 user port pins uart in uart out v keymatrix y3 y2 y4 y1 qs3125 i/o i/o i/o i/o i/o i/o i/o i/o e e e e 22v10 rt ct + _ + _
vgs. the mosfet should have an input capacitance (ciss) of under 50pf for low charge injection. components not shown are:  a +5 volt regulator (78l05 types are suitable);  supply bypass capacitors (two 0.1uf x7r caps placed near the 60320 and the 74hc4066's);  an rs232 level translator, like a max232 or comparable device to allow communications over a cable to a distant host device (if desired). 74hc4066 switches work fine but are less than ideal; these switches have high levels of charge injection that will add to the signal and also induce thermal drift. however these parts provide a break-before-make action that is critical to successful operation. see section 4 for more circuit specifics. 2.2 water suppressing circuit a circuit that suppresses cross-coupling from key to key by water films is shown in figure 2-2. this circuit includes a 22v10 type cmos pld configured with an rc timing circuit to shorten the dwell time of the y gate pulses. this has the effect of curtailing the charge collected from parts of a water film that are distant from the key, thus reducing the occurrence of cross-coupling among keys when the panel is wet. rt and ct are adjusted to provide a timing delay of from 75ns to 100ns. this circuit is employed in quantum's e6s3 eval board (section 5). the 22v10 creates a short delay from the rising edge of the x line in use; this delayed signal is gated with the y lines to create new, foreshortened y-gate signals (figure 2-3). a qualitysemi qs3125 'bus gate' (also: ti sn74cbt3125, pericom pi5c3125 or comparable) is used as a high performance n-channel analog switch having near-zero charge injection. the switch is only used as a charge drain to near-ground potential, and so full bilateral 0-5v switch operation is not required. source code for the 22v10 can be found in section 5. representative parts include the xilinx xcr22v10 and ict's peel22cv10ac-25. this device must have conventional cmos i/o structures to work properly. mechanical measures can also be used to suppress key cross-coupling, for example raised plastic barriers between keys (or placing keys in shallow wells) to lengthen the electrical path from key to key, or simply increasing the key spacing (and reducing key size). see section 4 for more circuit specifics. 2.3 calibration the 60320 calibrates on power-up using algorithms that seek out the optimal level of r2r offset and cz cancellation on a key-by-key basis. the algorithm uses a successive approximation method, to calibrate all 32 keys in about one second. the calibration data is not permanently stored; the device recalibrates each time the unit powers up. if a false calibration occurs due to a key touch or foreign object on the keys during powerup, the affected key will recalibrate again immediately when the object is removed. a calibration cycle can also be induced via a serial command from a host device. 2.4 x-y timing the basic timing diagram shown in figure 2-3 relates to a particular key being addressed by an x a drive line and a gate control line y b . the acquisition of a key is done using a discrete burst of x pulses of length 'n', where 'n' is programmable via the uart interface (and stored internally in eeprom). the corresponding y line for the sampled key is also pulsed in quadrature so as to gate the external analog switch, straddling the rising edge of xa. at the end of the burst, the x pins are used to drive the external r2r ladder network which generates an offset to the amplifier chain. it is during this period that the amplifier stabilizes and the signal is sampled internally by the qt60320. figure 2-3 also shows a dwell-adjusted version of yb, yb', that can be generated with the help of external timing delays. yb' has a shortened dwell time with respect to xa; this shorter dwell time acts to suppress the effects of moisture on the keyboard surface by foreshortening the charge transfer process, which acts to limit the recovery of charge forced into the water film by the rising edge of xa. yb is used to gate another analog switch to ground, and if the switches used do not have a break-before-make characteristic, they should be guard-banded as shown to prevent cross conduction from cs to ground. 3 serial interface the qt60320 uses a serial interface to a host. this port uses a simple ascii protocol described in this section. 3.1 serial port specifications the qt60320 uses a full-duplex asynchronous serial interface with the following specifications: baud rate: 9600 parity: none length: 8 bits stop bits: 1 these specifications hold if the device is operated from an 8mhz crystal or resonator. l q 6 qt60320c r1.08/01.03 figure 2-3 timing of x and y signals yb xa amp out 'n' pulses / burst r2r value xa yb yb' yb
the port can be directly connected to a like port of a host mcu, or transmitted over a length of cable on a standard rs232c interface to a pc or other device, with the aid of a max232 type driver/receiver circuit. 3.2 command set the 60320 requires ascii commands over the serial port in order to send result data. the commands must be one of those listed in table 3-1. none of the commands should ever be terminated with a cr or lf code. each command is self-contained and requires no terminator. 3.2.1 's' c ommand - b utton s tate (hex code 0x73) after an ?s? character is received, the e6s3 reports back the touch-state of the buttons; it responds by transmitting back 4 bytes of data containing a total of 32 data bits, where each bit represents the state of one button (table 3-2). each byte holds the state of the buttons contained in a y column. the first byte corresponds to column y1 while the 4th byte corresponds to column y4. bit 0 of each byte holds the state of the button corresponding to x1; bit 7 holds the state corresponding to x8. multiple key presses will show as multiple bits being set in the data stream. the device supports n-key rollover to a limit of all 32 keys. example: the key at intersection x5/y2 appears at bit 4 in the second byte; if key x5/y2 is touched the bit is set. all untouched bits register as a ?0'. 3.2.2 's' c ommand - i dentification r eporting (hex code 0x53) the e6s3 board responds with the 7-byte ascii signature "32000xx" where x is the code revision. 3.2.3 'e' c ommand - e rror r eporting (hex code 0x65) this command allows the host to retrieve the error status bits for all buttons, in 4 consecutive bytes (table 3-3). the byte and bit sequences are identical to that described in conjunction with the 's' command (see prior). the appropriate bits are set high when errors are detected. the error may be caused either by a short across the button or an open circuit at the button. 3.2.4 '/dxy' c ommand - d ata s ignal r eporting (hex codes 0x2f 0x64 x y) this sequence reports back the signal level and reference value for the key chosen. x and y are zero-referenced binary (not ascii) values in the range 0..7 for x and 0..3 for y to indicate the button for which data is requested. if x=0 and y=0, the device reports back with the data for key x1 y1. if x=3 and y=1, the key selected is x4 y2. the last key is x8 y4, so the highest /dxy command is /d73 where '7' and '3' are in binary. the device reports back with two bytes: the first is the reference level, the second is the signal level. both are binary bytes of range 0..255. 3.2.5 '/dxy' c ommand - o ffset & c oarse r eporting (hex codes 0x2f 0x44 x y) this sequence reports back the fine offset (r2r dac) and coarse (cz1, cz2 bucking caps) values for the key chosen. x and y are zero- referenced binary (not ascii) values in the range 0..7 for x and 0..3 for y to indicate the button for which data is requested. the device reports back with two bytes: the first is the r2r offset dac amount (0..255), the second is the coarse setting as a bit pattern: coarse bit 0 corresponds to cz1, coarse bit 1 to cz2, resulting in valid data values of 0, 1, 3. this information is useful in observing circuit behavior for diagnostic purposes during development. values of coarse = 3 and offset > 128 indicate excessive x-to-y coupling that can arise due to normal production variances or component drift. the maximum limit the circuit can tolerate is coarse = 3, offset = 255 before the signal saturates and a key becomes inoperable. 3.2.6 '/ea' c ommand - s ettings r eporting (hex codes 0x2f 0x65 a) allows the gain and threshold settings for a specific button to be read back to the host. 'a' is a single binary byte specifying the address of the data to be read. separate commands must be issued to read the gain and threshold for each button as these values are held at separate addresses, with the data for the threshold being held in the address immediately following that for the gain. the gain and threshold settings for all buttons are held in an internal byte array, starting at address 100 (decimal). l q 7 qt60320c r1.08/01.03 table 3-1 ascii command set port read. reads back the 4 bits of user port pins i1..i4 0x49 i port write. writes byte value v to the user output pins o1..o8 0x4f v ov settings write. writes the gain or threshold value v for the chosen key at a 0x2f 0x45 a v /eav settings reporting. returns gain and threshold levels for chosen key at a 0x2f 0x65 a /ea offset,coarse cal reporting. returns coarse and offset values for the key at location x y 0x2f 0x44 x y /dxy data signal reporting. returns signal and reference for the key at location x y 0x2f 0x64 x y /dxy error reporting. returns 4 bytes corresponding to error bits for each key 0x65 e identification command. qt60320 responds with signature "32000xx" where xx is the code revision 0x53 s button state. returns 4 bytes of on/off status for all buttons 0x73 s purpose hex code ascii code table 3-2 's' command button state responses x1/y4 x2/y4 x3/y4 x4/y4 x5/y4 x6/y4 x7/y4 x8/y4 4 x1/y3 x2/y3 x3/y3 x4/y3 x5/y3 x6/y3 x7/y3 x8/y3 3 x1/y2 x2/y2 x3/y2 x4/y2 x5/y2 x6/y2 x7/y2 x8/y2 2 x1/y1 x2/y1 x3/y1 x4/y1 x5/y1 x6/y1 x7/y1 x8/y1 1 byte # 0 1 2 3 4 5 6 7 bit #
the first two sequential bytes in this array hold the settings data for button x1/y1, the next two bytes hold the data for button x2/y1 and so on. the gain is held in the first byte (at the lower address) and the threshold in the second byte. the button memory addresses are calculated as follows for a given key: multiply (x-1) times 2 to get m so, if the key is on x6, m = (6-1)*2 = 10 (decimal). multiply (y-1) times 16 to get n so, if the key is on y3, n = (3-1)*16 = 32 (decimal). add m + n + 100 to get the first of the two memory addresses for the key. example: a key located at x4, y3 would have its base address at: (4-1)*2 + (3-1)*16 + 100 = 32 + 6 + 100 = 138 (decimal) the first byte, at address 138 decimal is the gain, while address 139 has the threshold for x4/y3. the address must be sent as a binary number (packed into 8 bits, i.e. 0x8a and 0x8b in this example), not as the ascii string ?1 3 8?. the qt60320 reports back with a single binary byte containing the data requested. 3.2.7 eeprom r ead a ccess via /ea it is possible to use part of the qt60320's internal eeprom as 'user storage'. this feature allows the elimination of a separate eeprom associated with a host mcu, reducing system cost. the qt60320 has 86 bytes of spare eeprom available to the user for any function whatsoever. the eeprom can be read and written using the same /ea and /eav commands used to examine and write key settings. the first byte of eeprom is located at address 170 (decimal) and can be read via the command string /ea where 'a' is the binary byte 170 (0xaa). the highest location is at 255 (0xff). 3.2.8 '/eav' c ommand - s ettings w rite (hex codes 0x2f 0x45 a v) allows the gain and threshold settings for a button to be written. 'a' is a single binary byte specifying the address and 'v' is a single binary byte value of the data to be written. the addresses are calculated in an identical manner to those for the /ea command above. note that a change in the gain value of even one key will cause the e6s3 to recalibrate all keys. 3.2.9 eeprom w rite a ccess via /ea v see 3.2.7 for information on reading eeprom data. the /eav command can be used to write a byte to any of the 86 available internal eeprom locations. like the /ea command, byte 'a' is the address of the byte from 0xaa to 0xff. the byte 'v' should contain the 8-bit binary data to be written to the address 'a'. the first byte of eeprom is located at address 170 (decimal) and can be written via the command string /ea where 'a' is the binary byte 170 (0xaa). the highest location is at 255 (0xff). 3.2.10 'ov' c ommand - u ser p ort w rite (hex codes 0x4f v) writes the value ?v?, an 8-bit binary byte, to the qt60320?s 8 output port pins o1?o8. this feature can be used to drive led?s via external buffers, a self-oscillating acoustic sounder, or other peripheral device. it can even be used in conjunction with the ?i? command (below) to scan a set of external electromechanical keys (up to 32 switches, e.g. in an 8x4 matrix) near the panel. 3.2.11 'i' c ommand - u ser p ort r ead (hex code 0x49) causes the qt60320 to return a binary byte from the port pins i1?i4. the value is returned in the lower nibble (bits 0,1,2,3) of the return byte. the high 4 bits are held at zero. 4 - circuit guidelines 4.1 power supply, pcb layout the power supply should be 5.0 volts +/- 10%. this can be provided by a common 78l05 3-terminal regulator. ldo type regulators are usually fine but can suffer from poor transient load response; this will cause erratic key behavior. if the power supply is shared with another electronic system, care should be taken to assure that the supply is free of digital spikes, sags, and surges which can adversely affect the circuit. the qt60320 will track slow changes in vcc, but it can be adversely affected by rapid voltage steps and impulse noise on the supply rail. 4.2 sample capacitor charge sampler cs should be a pps film or npo ceramic type for best stability. acceptable cs values range from 1nf to 50nf. lower values will increase circuit gain and hence key sensitivity; lower values also act to reduce the required burst length for a given desired sensitivity at the expense of reduced inherent signal averaging. 4.3 c z capacitors the two cz capacitors should have a value of 4% to 6% of the total value of cs + cz1 + cz2. the objective is to allow the creation of a negative voltage step at cs of about 0.25 volts with each cz cap switched. in cases where the matrix is composed entirely of small keys, the cz caps may not actually fire, or perhaps only one of them may fire. however, the device's error detection logic requires the presence of these two capacitors in order to function correctly. if cs = 15nf (a common value for the circuit), then each cz should be 820pf. the cz capacitors should be of type npo or c0g ceramic, or pps film. l q 8 qt60320c r1.08/01.03 table 3-3 'e' command error code responses x1/y4 x2/y4 x3/y4 x4/y4 x5/y4 x6/y4 x7/y4 x8/y4 4 x1/y3 x2/y3 x3/y3 x4/y3 x5/y3 x6/y3 x7/y3 x8/y3 3 x1/y2 x2/y2 x3/y2 x4/y2 x5/y2 x6/y2 x7/y2 x8/y2 2 x1/y1 x2/y1 x3/y1 x4/y1 x5/y1 x6/y1 x7/y1 x8/y1 1 byte # 0 1 2 3 4 5 6 7 bit #
4.4 r2r resistor ladder the r2r resistor ladder network should be of value r=100k ohms and have a precision of at least 7 bits. the nominal resistance of the ladder is also the series impedance of the ladder and affects the scaling of the offset injected into the amplifier chain. the ladder should create an offset in the output of the amplifier chain of about 0.15 volts / lsb. the scaling of the offset injection also affects the crossover points for the switching of each cz capacitor. if during the calibration cycle the r2r network is found to not provide enough offset to bring the signal to the midpoint of the adc's range, a cz capacitor will be switched in to create an additional negative offset. if the r2r value and cz values are not properly matched, the circuit may not be able to converge on a calibration point. this will happen especially if the cz cancellation voltage step is too large. 4.5 amplifier the amplifier chain should be as shown in the various figures in this datasheet. it should have 2 stages of gain, totaling about 100 +/-20%. numerous opamps are available that will perform to requirements, including the ti tlc2272 and the analog devices opa2340. the opamps should have at least a rail-to-rail cmos output, and an input that can sense from ground to at least +1 volt. the recommended gbw is 2mhz or above. to reduce leakage current problems the amplifier should be a jfet or cmos input type only. 4.6 esd protection in general the qt60320 will be protected from direct static discharge by the overlying panel. however, even with a panel, transients can still flow into the electrode via induction, or in extreme cases, via dielectric breakdown. porous materials may allow a spark to tunnel right through the material. testing is required to reveal any problems. the qt60320 does have diode protection on its terminals which can absorb and protect the device from most induced discharges, up to 20ma; the usefulness of the internal clamping will depending on the dielectric properties, panel thickness, rise time of the esd transients, and their duration. the device pins can be further protected by inserting series resistance into the x lines; similarly, the charge capture circuitry (the pld and analog switch) can similarly benefit from series-r in the y lines. the resistances chosen should not be so high as to interfere with the qt process. every board layout is different and thus it is difficult to specify a suitable value, however, typical values range from 200 ohms to 10k ohms. in serious cases additional low-capacitance high-conductance clamp diodes (e.g. bav99) may be added to shunt esd aside. the qt60320's 'x' drive lines are always being driven at low impedance; they are never 3-state unless the circuit is powering up or is powered down. this is a considerable advantage in dealing with esd. the part's y control pins do not directly go to the matrix. the 4 user-input pins may be vulnerable and should be resistor and/or diode protected if they are in danger of being subject to esd. l q 9 qt60320c r1.08/01.03
5 epld source listing source listing for a ict peel22cv10az epld . the epld functions to generate control signals for the qs3125 quad n-channel switch, to clamp unused y lines during scanning, and to control the y gate dwell time after the rise of an x line. this latter feature all ows for moisture suppression since the charge transfer duration decreases (and thus is less responsive to the slow-moving charges from resistive water films) with decreasing dwell time. rt and ct (r21 and c12 in the e6s3) govern this delay time after the rise of any x line. _________________________________________________________ title 'e6s3' designer 'h philipp & s brunet' date '12/03/01' peel22cv10a "i/o configuration declaration "ioc (pin_no 'pin_name' polarity output_type feedback_type ) "inputs xs1 pin 8 "externally or'd x inputs (8) xs2 pin 7 xs3 pin 6 xs4 pin 5 xs5 pin 4 xs6 pin 3 xs7 pin 2 xs8 pin 1 ys2 pin 9 ys3 pin 10 ys4 pin 11 ys1 pin 13 "outputs "clamping outputs ioc ( 22 'y1' pos com feed_pin ) ioc ( 20 'y2' pos com feed_pin ) ioc ( 19 'y3' pos com feed_pin ) ioc ( 17 'y4' pos com feed_pin ) "qs3125 drives ioc ( 23 'f1' pos outcom feed_pin ) ioc ( 21 'f2' pos outcom feed_pin ) ioc ( 18 'f3' pos outcom feed_pin ) ioc ( 16 'f4' pos outcom feed_pin ) "dly ckt in (& reset of delay cap drive out) ioc ( 14 'xsd' pos com feed_pin ) "dly ckt drive out ioc ( 15 'xss' pos outcom feed_pin ) ar node 25 "global asynchronous reset sp node 26 "global synchronous preset equations ar = 0; sp = 0; y4.com = 0; " clamp outputs y3.com = 0; y2.com = 0; y1.com = 0; y4.oe = !ys4; " drive outs to gnd when not used. y3.oe = !ys3; y2.oe = !ys2; y1.oe = !ys1; xss.com = xs1 # xs2 # xs3 # xs4 # xs5 # xs6 # xs7 # xs8; "sum all of x to drive out delay ckt xsd.com = 0; xsd.oe = !(xs1 # xs2 # xs3 # xs4 # xs5 # xs6 # xs7 # xs8); "clamp the delay cap when all 'xs' lines are 0 f4.com = !(ys4 & !xsd); " enables to 3125 are active low f3.com = !(ys3 & !xsd); f2.com = !(ys2 & !xsd); f1.com = !(ys1 & !xsd); l q 10 qt60320c r1.08/01.03
6 e6s3 board schematic l q 11 qt60320c r1.08/01.03
7.1 absolute maximum specifications operating temp ................................................................. as designated by suffix storage temp .........................................................................-55 o c to +105 o c v dd .................................................................................... -0.5 to +6.0v max continuous pin current, any control or drive pin ................................................ 20ma short circuit duration to ground, any pin ........................................................... infinite short circuit duration to v dd , any pin .............................................................. infinite voltage forced onto any pin ..................................................... -0.6v to ( vdd + 0.6) volts 7.2 recommended operating conditions v dd ................................................................................... +4.75 to 5.25v supply ripple+noise ..................................................................... 20mv p-p max load capacitance ........................................................................... 0 to 20pf cs value................................................................................ 10nf to 30nf 7.3 dc specifications vdd = 5.0v, cs = 15nf, ta = recommended range, unless otherwise noted bits 8 acquisition resolution a r a 1 input leakage current i il 1ma source v vdd-0.7 high output voltage v oh 4ma sink v 0.6 low output voltage v ol v 2.2 high input logic level v hl v 0.8 low input logic level v il ma 25 supply current i dd notes units max typ min description parameter l q 12 qt60320c r1.08/01.03
8 mechanical 8.1 dimensions 8.2 marking l q 13 qt60320c r1.08/01.03 1 2 3 4 8 7 6 5 11 10 9 33 32 31 30 28 23 24 25 26 27 29 12 14 16 18 22 20 15 17 19 21 13 44 42 40 38 36 34 43 41 37 39 35 symbol a e e h h l p p a millimeters inches min max notes min max notes e h h a e p a l o 12.21 11.75 0.458 0.478 0.09 0.20 0.003 0.008 0.45 0.05 0.75 0.15 1.20 0.018 0.002 0.030 0.006 0.047 0.80 0.30 bsc 8.00 0.80 0.45 0.031 0.012 bsc 0.315 0.031 0.018 9.90 10.10 0.386 0.394 - - o07 07 p bsc bsc sq sq sq sq package type: 44 pin tqfp 8.00 0.315 qt60320c-a QT60320C-AS -40 0 c to +105 0 c marking tqfp t a
l q copyright ? 2002 qrg ltd. all rights reserved. patented and patents pending corporate headquarters 1 mitchell point ensign way, hamble so31 4rf great britain tel: +44 (0)23 8056 5600 fax: +44 (0)23 8045 3939 admin@qprox.com www.qprox.com north america 651 holiday drive bldg. 5 / 300 pittsburgh, pa 15220 usa tel: 412-391-7367 fax: 412-291-1015 the specifications set out in this document are subject to change without notice. all products sold and services supplied by qrg are subject to our terms and conditions of sale and supply of services which are available online at www.qprox.com and are supplied with every order acknowledgement. qprox, qtouch, qmatrix, qlevel, and qslide are trademarks of qrg. qrg products are not suitable for medical (including life-saving equipment), safety or mission critical applications or other simil ar purposes. except as expressly set out in qrg's terms and conditions, no licenses to patents or other intellectual property of qrg (express or implied) are granted by qrg in connection with the sale of qrg products or provision of qrg services. qrg will not be liable for customer product design and customers are entirely responsible for their products and applications which incorporate qrg's products.


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